In Depth Parasitic Capacitance Analysis on GaN-HEMTs with Recessed MIS Gate

: In this study, parasitic coupling capacitance behavior on GaN devices with recessed MIS-gate is analysed in depth by combining experimental data, 2D-simulations, analytical calculations, and TEM imaging. This enabled to highlight the second channel formation. A new analytical model to determine the contribution of the active channel and the different coupling parasitic capacitances from a gate-to-channel capacitance C gc curve of a GaN MIS-HEMT is proposed. This also enables the evaluation of the respective contributions of all components such as the passivation layer and gate field plate capacitances in the parasitic capacitance and effective gate length evaluation of GaN devices with recessed MIS gate, which could be useful for reliable parameter extraction, device modeling and optimization.


Introduction
Heterojunction device-based AlGaN/GaN High Electron Mobility Transistors (HEMTs) have attracted a lot of attention in power electronics and RF applications, which require high breakdown voltage and low ON-resistance [1][2][3][4][5]. With the fast development of GaN-based-device technology and circuit integration, reliable predictive models are of great value for circuit design and simulation [6]. The capacitance-voltage (C-V) characteristics, which are equally important for circuit simulation and modelling, have received less attention for GaN devices in the last decade. However, with the progressive miniaturization of these GaN devices for power electronics and RF circuit, different parasitic effects must be considered for a reliable device modelling and simulation [6][7][8][9]. For silicon technology, several methodologies have been proposed to analyse the parasitic components [10,11], but this is less the case for GaN devices.
In previous studies [4,12], gate-to-channel capacitance was measured and simulated for different gate lengths and recess depths. We proposed here a new methodology to extract the coupling parasitic components and effective gate length from gate-to-channel capacitance C gc measurements. Zhang et al. [6] have reported the analytical modeling of capacitances for normally-On HEMTs, including parasitic components. However, few works have been dedicated to the effects of etching depth and device architecture on gate-to-channel coupling capacitance.
In this study, we present, for a first time, a new approach to analyse the C gc characteristics of a GaN MIS-HEMT with recessed gate and to discriminate the active channel and parasitic capacitances. This will enable us to evaluate the electrical length of the active channel under the gate. We will first summarize the experimental details of this study, such as process technology, device architecture and electrical characterization protocol. Next, we will update a previous work on gate-to-channel capacitance measurements and 2D-simulation methodology of interest for this study [12]. We will also show the coupling capacitance variations and the formation of a second channel, observed in the simulated structure. All experimental and analytical methods, including various recess depths, have been validated with 2D simulations and were used to evaluate parasitic capacitances. Finally, we will compare the respective impact of parasitic channel length on C gc capacitance and their influence on the extraction of the effective gate length of the active channel.

Device and Experimental Setup
We conducted the electrical measurements on two different wafers processed with normally-off GaN MIS-HEMT technology. GaN epitaxy (Figure 1a) was achieved by Metal-Organic-Chemical Vapor Deposition (MOCVD), on 200mm diameter silicon (111) substrates [12]. The structure consisted of an AlN nucleation layer, an AlGaN based buffer, C-doped GaN buffer layers to ensure a high breakdown voltage and of an unintentionally doped (UID) GaN channel in which a back-barrier could be inserted. The piezoelectric effect to form the 2D electron gas (2DEG) was obtained with the growth of AlN spacer and an Al x Ga 1-x N barrier layer on top of the GaN channel layer, followed by in-situ deposition of a passivation layer [13,14]. In this study, fully recessed Metal-Insulator Semiconductor (MIS) gate normally-off GaN devices were processed by dry etching of AlGaN and UID-GaN layers in the gate area. Figure 1b shows a cross sectional TEM of the fully recessed MIS gate region with different typical interfaces. The two studied wafers correspond respectively to two different recess depths, i.e., a shallow gate recess (RD1) and a deep gate recess (RD2). The gate recess was followed by the deposition of an oxide layer of Al 2 O 3 by Atomic Layer Deposition and the metallic gate. The source and drain ohmic contacts were composed of Ti/AlCu metallic pads connected to the 2D electron gas (2DEG) formed at the AlGaN/GaN interface. The tested symmetrical T-gate devices have a gate field plate length of 0.25 µm (L FPg ) (Figure 1), 200 µm width (W) and channel lengths (L g ) ranging from 0.25 μm to 2 µm. The total gate-to-channel capacitance C gc was measured with a HP 4284 LCR meter. The "High" entry of the LCR meter was connected to the gate electrode with a 40 mV AC signal. The "Low" entry of the LCR meter was connected to the source and drain electrodes for the complex current measurement. The LCR-meter was calibrated using an open procedure in order to obtain the best accuracy for the capacitance measurements.

Methodology
The capacitance C gc (Equation (1)) was calculated using the total energy variation ∆W e (Equation (2)) of the device for each increment of gate bias ∆V g . It should be mentioned that this method was first used on FD-SOI device by Ben Akkez et al. [11] and was applied for the first time on AlGaN/GaN based devices in our previous work [12].
where ΔE is the local electric field variation, ΔV the local potential change, Δρ the local charge density difference for gate bias varying from V g to V g + ΔV g and ε the permittivity. The total energy variation is computed by integration of the electric field and space charge contributions over the device volume (Equation (2)) [11,15]. It is worth noting that, in Equation 2, the local electric field term (ε·ΔE 2 /2) prevails in dielectric-like regions with low charge density, whereas the local energy charge term (Δρ·ΔV/2) dominates in accumulation/inversion regions when free carrier concentration increases [12].

GaN MIS-HEMT Devices Simulation Results
The total gate-to-channel capacitance simulations have been carried out after solving the Poisson equation in a standard GaN MIS-HEMT device with recessed gate as shown in Figure 2. The simulated architectures were realized to match the TEM picture with different typical interface as those of Figure 1b. The GaN channel and AlGaN layers were taken as unintentionally doped (UID). The parameters used for the simulation are: σ GaN/AlGaN = 0.9 × 10 13 cm −2 , σ AlGaN/Passivation = 0 cm −2 and C ox = ε ox /t ox = 2.56 × 10 −7 F·cm −2 (for t ox ≈ 30 nm) [12]. The source and drain contact regions are electrically connected to the 2DEG, which is induced by the polarization charge at the AlGaN/GaN interface [16]. The electrons in the GaN and AlGaN layers are treated with classical Boltzmann statistics. The response of hole minority carriers is deactivated because it was not experimentally observed in these AlGaN/GaN devices. The source and drain ohmic contacts are grounded and the gate contact is DC biased to V g .
To fit the lateral position of the experimental capacitance characteristics C gc (V g ) with simulation result, the flat- Buffer-based AIGaN AIGaN Oxide L Fpg,D = 0.25µm D band voltage V fb was adjusted. The total gate-to-channel capacitance (C gc ) was simulated for symmetrical GaN MIS-HEMT devices (L GS = L GD = 2 μm) with the parameters indicated previously. Figure 3a shows that good fits between experimental and simulation results can be achieved for different gate lengths. In Figure 3b are reported the maximum (at −4 V) and minimum (at 4 V) C gc capacitances versus gate length for two different recess depths (RD1 and RD2). We can see the same minimum capacitance C gc for V g = −4 V and a linear dependence with L g for V g = 4 V. This confirms that the C gc in depletion regime (V g << V fb ) stems from the gate-to-2DEG coupling capacitance.
(a) (b)   Figure 4a,b present the electron density profiles in accumulation and depletion regimes. We can see a particular shape of the source (or drain) electrode and its variation with gate voltage. As was explained in [12], we observe that, in depletion, the 2DEG region ends at a certain point P ( Figure 4a) close to the oxide (Al 2 O 3 ) interface. Therefore, the minimum capacitance C min will come from the coupling between the source and drain contacts along the 2DEG located at the GaN/AlGaN interface up to its extremity at a certain point P and the gate contact. In accumulation regime, the 2DEG at source and drain sides are connected to the electron channel formed at the GaN/Al 2 O 3 interface. However, we can see that a second channel appears along and above the AlGaN/Al 2 O 3 interface as well as at the AlGaN/passivation interface (depending on gate bias, field plate length and polarization charge at this interface). Figure 4c,d show the potential profile and equivalent capacitance circuit for the different coupling areas in the gate region of a GaN HEMT device in depletion and accumulation regimes. The equipotential lines illustrate how the potential changes from source to gate contacts across the device. The electrostatic coupling is stronger in region where the potential drop is more abrupt. A coupling capacitance appears at negative gate bias due to the coupling between the horizontal source or drain electrodes formed by 2DEG and the gate electrode. Figure 4d shows that the coupling in accumulation stems from the coupling between the electron channel and the gate contact. The parasitic electron channel can extend along the AlGaN/Al 2 O 3 interface farther than the effective channel L eff (Figure 4b). These results agree with our previous results [12].
Moreover, a parasitic electrostatic coupling exists between the gate field plate and the electron channel at the AlGaN/passivation interface (Figure 4b). Therefore, a simulation study and an electrostatic coupling analysis above the 2DEG is necessary to evaluate the parasitic coupling capacitances, for further correction. Deep

Dielectric Behavior Analysis of Parasitic Coupling
As our main concerns are parasitic coupling capacitance C Par and effective gate length L eff , we will focus mainly on the analysis of parasitic capacitance in accumulation (Figure 4b,d). To simplify the simulation, the 2DEG has been replaced by a metal strip and the channel at Al 2 O 3 interface or AlGaN/passivation interface by another metal strip ( Figure  5). We define the length x as the extension length of the second channel formed at the AlGaN/passivation interface from the AlGaN/Al 2 O 3 interface. We can see its appearance in Figure 4b, but its extension may depend on many parameters (such as the gate field plate length, the bias and the polarization charge). Therefore, we will study the influence of this extension length x on parasitic coupling capacitances.
We also replaced the different semiconductor layers by dielectric layers having each time the same dielectric constant. The total capacitance was computed from Equation (1) where the total energy (Equation (2)) becomesε·εΔE 2 /2. Figure 5 shows the potential map and corresponding equivalent circuit of the coupling capacitance between metal and contact channel. Using different extension length x and δL/2 values, simulations allow us to estimate the parasitic coupling capacitance between the gate edge above the 2DEG and the access regions. In order to extract the parasitic capacitance from the simulation reported in Figure 5, we write: where t Pass and t AlGaN are the thickness of passivation and AlGaN layers respectively. C ox ·(L g + δL)/2 is the effective oxide capacitance (F/cm) in the active channel and C C (0,x,θ,t pass ,t AlGaN ) stands for all parasitic coupling capacitances. δL/2 is the gate side wall length, C ox the oxide capacitance, θ the gate side wall angle and x the extension length of second channel. Figure 6a shows the coupling capacitance C Computed (δL/2,x,θ,t pass ,t AlGaN ) at source side versus channel edge length δL/2 for various channel extension lengths x. The coupling capacitances depend linearly on δL/2 (Figure 6a) confirming the validity of Equation (3) definition. Therefore, C C (0,x,θ,t pass ,t AlGaN ) can be considered as a correct evaluation of coupling capacitance at source side. We must keep in mind that in the experimental measurements, the parasitic capacitance C Par corresponds to parasitic coupling at both source and drain edges, which leads us to Equation (4).
(4) Figure 6b shows the evolution of the different component of the parasitic coupling capacitance, C C (0,x,θ,t pass ,t AlGaN ) with the extension length x. C C starts from 2.01 × 10 −12 F/cm for x = 0 µm to 2.75 × 10 −12 F/cm.

Journal of Electronics and Electrical Engineering
As a result, we propose in Equation (6) a simple model to estimate the parasitic coupling capacitance values C C (0,x,θ,t pass ,t AlGaN ).
, G T where are the coupling capacitances between gate field plate and electron channel at AlGaN/GaN or AlGaN/passivation interfaces, respectively. C A1 O 2 3 is the oxide capacitance (F/cm 2 ), C Pass the passivation capacitance (F/cm 2 ) under the gate field plate and C AlGaN the AlGaN layer capacitance. All of them follow C = ε/t where ε and t are dielectric constant and thickness of each layer. In Equation (6), the first term C FPg,1 ·(L FPg,S -x 2 ) + C FPg,2 ·(x 2 ) is the coupling capacitance between the gate field plate and the electron channel, and it increases from 1.05 × 10 −12 F/cm (if x = 0) to 1.2 × 10 −12 F/cm for x > t t L FPg S AlGaN P ass sin( ) tan( ) Depending on x 2 , C FPg accounts for 45% to 53% (x 2 = 0) of the total parasitic coupling. The second term C A1 O 2 3 ·x 0 is the Al 2 O 3 layer coupling between the gate edge and electron channel at AlGaN/Al 2 O 3 interface, which increases from 0 to 7.42 × 10 −13 F/cm when the whole parasitic channel is formed, accounting then for 27.5%. The third term C 2D corresponds to the coupling between the gate field plate corner and access regions, it depends weakly on x 3 , accounting for 14-15% of total parasitic capacitance. The last term C δ (x 0 ,x 1 ,θ,t Pass ,t AlGaN ) is also a 2D coupling but this time in the proximity of the active channel, mainly in the extension regions corresponding to x 0 and x 1 . It was obtained by subtracting all the previous contributions to the total coupling capacitance C c (Figure 6b). C δ accounts for 30% of the parasitic coupling in the case of no parasitic channel (x = 0) but decreases and saturates quickly to 14%, as the parasitic channel increases. It should also be noted that, as the channel x 0 is formed along Al 2 O 3 interface, the increase of C A1 O 2 3 from 0 to 27.5% is compensated by the decrease of C δ , and the sum of them only varies from 30% to 41.5%. Thus, the variation of capacitances with x are moderate and the previous simulation (Figure 4b) has shown the formation of a parasitic channel in x 0 and x 1 regions.
After studying the total parasitic coupling capacitances C C (0,x,θ,t Pass ,t AlGaN ) by simulation or by the model of Equation (6), we can use the experimental capacitance measurements to estimate the difference ΔL 0 (x) between the effective gate length L eff and gate length L g . We use the expression L eff (x) = [C max / W -C Par (x)] / C ox (W in cm) [12], where C max is the measured maximum capacitance and C Par (x) the simulated or modelled parasitic coupling capacitance [Equation (4)] for a 1 cm structure width. Figure 8 shows different values of ΔL 0 (x) = L eff (x) − L g versus gate length L g for shallow and deep gate recess gates. The dashed lines in Figure 8 represent ΔL 0 measured by TEM, ΔL 0,TEM = L eff,TEM − L g (where L eff,TEM = L bottom + 2(δL/2) obtained on MIS structures with 0.25 µm gate length for the deep gate recess wafer and a 0.5 µm gate length for the shallow gate recess wafer. We can see the good agreement between TEM physical extraction and simulation results, confirming the consistency of our study. Full device simulations ( Figure 5) show the formation of a parasitic channel and the calculation of parasitic simulation [C Par (x)] agrees with the estimation of effective channel by TEM (ΔL 0,TEM ) measurement, especially when this parasitic channel is formed.  Figure 9 reports a CV measurement for a short channel GaN MIS-HEMT device with a deep gate recess (RD2), we can notice a double plateau behavior in the accumulation regime (note that this hump was also observed for RD1 device). This behavior is only visible on the shortest gate lengths for which it represents approximately 10% of the maximum capacitance. It could be due to the formation of the parasitic channel observed in simulation. The difference ΔC gc = [C gc (V g = 2V) − C gc (V g = 5V)] / W is around 1.3 pF/cm (0.026 pF). This value is close to the parasitic coupling between gate and second channel, C x C x t t A1 O P ass A1GaN , obtained by simulation (1.2 pF/cm) confirming the hypothesis of such parasitic channel.
For a pragmatic use of this approach, capacitance measurements on a GaN MIS-HEMT device in accumulation can be employed to evaluate the effective channel length as long as the C Par contribution to the effective channel capacitance is well understood and estimated. Two approaches are possible to estimate C Par . It can be evaluated either by a full 2D semiconductor simulation (Figure 2) or using the analytical model proposed in Equation (6). We can also estimate C Par on a specific structure using TEM analysis on a same MIS device for which capacitance measurement is also performed, based on maximum capacitance C max in accumulation and L eff,TEM . The parasitic capacitance is then obtained by C Par = C max − C ox ·W·L eff,TEM . Figure 9a,b show the corresponding equivalent circuit of the various capacitances discussed previously in depletion and accumulation regimes. We indicated the location of gate-to-channel, gate-to-source and gate-to-drain capacitances, respectively C gc (see Figure 9b), C gs and C gd (see Figure 9a).

Conclusions
An in-depth analysis of parasitic coupling has been performed on GaN-HEMT devices with two different recess depths (RD1 and RD2) and various gate lengths. Extensive experimental capacitance analysis was com-pleted and compared to 2D numerical simulations. A simple analytical model of the parasitic capacitances occurring at HEMT edges has been developed and validated with numerical simulations. The simulations also show the formation of parasitic channels at AlGaN/Al 2 O 3 and AlGaN/Passivation interfaces. Moreover, the simulations clearly support the observation of different experimental parasitic capacitances observed both in depletion and in accumulation of electron channels. The proposed analytical model well predicts and explains the parasitic capacitance values and could be useful for reliable parameter extraction, device modeling and optimization. Finally, the results enable a reliable evaluation of the difference between the effective channel length (L eff ) and the gate length L g , which is in very good agreement with physical lengths extracted from TEM images.

Acknowledgments
This work was partially supported by the French Public Authorities within the frame of the PSPC French national program "G-mobility".

Data Availability Statement
The Figures data used to support the findings of this study are available from the corresponding author upon request