Performance Optimization of Carbon Nano-Tube Field Effect Transistors by Tuning Parameters

: As transistors are scaled down to keep up with Moore's law, the semiconductor industry is facing several challenges due to the limitation of traditional Metal Oxide Semiconductor Field Effect Transistor (MOSFET) technology. To overcome this issue of scalability, various other technologies are being researched. Among them are Carbon Nano-Tube Field Effect Transistors (CNTFET), Ribbon Field Effect Transistors (RibbonFET), Graphene Nanoribbon Field Effect Transistor (GNRFET), and Fin shaped Field Effect Transistor (FinFET), which can substitute MOSFETs. Due to carbon nanotubesʼ excellent conductivity supremacy, CNTFETs are a promising new solution. However, implementing a CNTFET and making circuits from it is still challenging as CNTFETs can exhibit properties of both semiconductor and metal depending on various parameters. This paper will illustrate the characteristics of the CNTFET, compare the power consumption and propagation delay of basic logic gates made using the CNTFET and MOSFET technology. The parameter tuning is done by measuring the power and delay for all parameter values. The Simulation of CNTFET is done on the Stanford CNTFET model using H-Spice.


Introduction
A Carbon Nanotube (CNT) is a cylindrical rolled structure of a graphene sheet, an allotrope of carbon. Transistors made using CNT as the channel between source and drain, are known as CNTFET. The CNT is divided into two types, namely the Single-Walled CNT (comprising of one CNT between the source and the drain), and Multi-walled CNT (coaxial set of multiple hollow CNTs between the source and the drain). CNTFET has the physical channel, unlike the conventional MOSFET, where the channel is induced between the source and the drain due to the applied gate voltage [1].
With respect to the structural arrangement, the carbon nanotube is further classified as i) Armchair, ii) Zigzag, and iii) Chiral. The semiconducting or metallic properties of CNTs are determined by the structural arrangement of the CNT atom and chirality, i.e., a combination of chiral vector and chiral angle. The CNTs are metallic if the chiral index, follows the condition m = n or m−n = 3i, where i is an integer, while for other values of m and n vector, CNTs are semiconductors. The conductivity of CNTs is around 80 times higher than that of copper, and the electron and hole mobility is better than silicon, resulting in quasi-ballistic charge carrier transport in a carbon nanotube. With all the promising features of CNTFETs, this device seems advantageous over traditional MOSFET devices in terms of propagation delay and Power Delay Product (PDP).

Literature Review
As we continue scaling down MOSFETs, various undesirable effects, like source to drain tunneling and shortchannel effects (SCE) due to decrease in gate length and lack of control over leakage current, are introduced. The mobility of electrons is also impacted when the channel length is decreased in MOSFET due to scattering effects such as surface roughness scattering, phonon scattering, coulombic scattering from the interface, and bulk charge impurity scattering [2]. Furthermore, there is an increase in gate oxide current leakage when the thickness of the gate oxide layer is reduced. In contrast, in the CNTFET, we do not observe any such side effects. Instead, it performs better due to the ballistic transport of charge carriers for smaller channels and gate lengths [3].
Furthermore, CNTFETs also have good dielectric properties, which can carry large currents in smaller volumes, increasing the current mobility. SCE and scattering mechanisms do not affect CNTFETs. CNTFETs look promising in overcoming the challenges faced by MOS transistors in reducing the size of transistors. Nevertheless, it is still challenging to fabricate CNTFETs and requires extensive research to optimize the parameters to make commercial circuits available in the market. The current mobility, dielectric, and conductivity are highly influenced by the change in parameters of CNT devices. Physical parameters like chirality, channel length, diameter, pitch, gate length, gate width, oxide thickness, supply voltage, and number of tubes influence the performance of CNTFET [4,5].
Different optimization schemes and models for CNTFET are proposed to overcome the effects of parasitic capacitances and obtain good-performing CNT-based transistors [6,7,8,9]. Furthermore, CNT-based transistor devices show minor differences in characteristics when multiple transistors exist in circuits with different arrangements. One of the most critical parameters that affect CNTFET's behaviour is the chirality of the carbon nanotube. In simpler terms, chirality defines the length and the angle at which the graphene sheet is cut to be rolled up in a Carbon Nano Tube. Chirality comprises of two components, the chiral vector, defined as Ch, and the chiral angle, defined as Ɵ. Based on the chiral vector, a CNT can behave either as a metallic or semiconducting CNT. The CNT diameter is also critical, as it determines the bandgap, affecting the electrical conductivity and threshold voltage for CNTFETs [10].
There are mainly three kinds of CNTFETs depending on the mechanism, SB-CNTFET (Schottky Barrier CNTFET), Partially Gated (PG-CNTFET), and MOSFET like CNTFET. SB-CNTFET incorporates a planar carbon nanotube connecting the metal source and drain. This connection between metal contacts and carbon nanotubes creates a Schottky barrier at the point of intersection. While MOSFET-like CNTs are four-terminal transistors, partial CNTs across the transistor's channel, source, and drain are heavily doped semiconductors (P-type or N-type). The mechanism of this device is like traditional four-terminal MOS transistors. The MOSFET-like transistors are more advantageous over the Schottky barrier CNTFETs such as low leakage currents due to the absence of the Schottky barrier, unipolar characteristics, higher conductivity, and current capacity to reduction in thickness of the potential barrier [11]. Thus, in this research, we will simulate the behaviour and compare the performance of MOSFET like CNTFET with CMOS transistors.
This paper describes CNTFET behavior by varying various parameters and comparing the results with traditional MOSFET technology. Characteristics such as delay, leakage current, supply voltage, and average power will be discussed for basic logic gates that can be used to make combinational circuits. For changing the parameters of CNTFETs, some measures must be considered as the change in one parameter also changes the other related parameters. An inappropriate change in the parameter value may result in incorrect functionality and behavior of the model, leading to false simulation results. Stanford University designed one of the most accurate models after experimenting with the properties of CNTs at the quantum level [12]. We have used this model of CNTFET to compare the performance of CNTFET devices with CMOS devices.
Here are some default parameters shown in Table 1, used in the CNTFET Stanford model that can be optimized for better propagation delay, power, and leakage current results. For observing the impact and optimization of CNTFET, we considered changing parameters such as Pitch, chirality, dielectric constant, number of tubes, and T OX . Pitch is the distance between two adjacent tubes in CNFET, and T OX is the thickness of top gate dielectric material, while K OX is the dielectric constant, subject to the material used in CNTFET. We randomly varied these parameters for the experiment and observed their effect on power consumption. The dielectric material enhances CNTFET's molecular properties and is used as a gate dielectric [13]. Different materials have been considered for CNTFET, such as SiO 2 , HfO 2 , TiO 2 , etc.; all these materials have a different dielectric constant value.

CNTFET Optimization
For optimization of CNTFET in terms of delay, static power, and dynamic power, we have changed one parameter of CNTFET at a time and recorded the performance for each parameter. For all these parameters, different values are recorded for three logical gates. All simulations are carried out at V DD = 0.9V using H-spice. The parameters we considered for optimization of CNTFET were Chirality, Pitch, number of tubes, and dielectric constant K OX of CNTFET. In the end, we have calculated the PDP for CNTFET as it is considered the best measure to check the performance of any transistor. We have also compared the optimized value of CNTFET with traditional transistors.

Delay Optimization for CNTFET
Delay time and switching speed are essential parameters for any transistor to improve the performance of electronic circuits. Propagation delay in transistors is the switching speed or time that a transistor takes to change the output signal to move from high to low or vice-versa with a change in the input signal. Several factors such as contact resistance, conductance, channel mobility, and reduced drain-induced barrier lowering affect propagation delay in transistors. In CNT, the configuration of connecting tubes can vary the conductance resulting in a change in the contact resistance; this can improve the switching speed and propagation delay in CNTFET. We have simulated the CNFET standard 32nm model and optimized the parameters to observe the effect of delay with change in parameters. The propagation delay of MOSFET shown in Table 2 is also calculated using H-Spice to compare its performance with optimized CNTFET. Propagation delay for CNTFET by varying parameters is shown in Tables 3-7. Lastly, after calculating the delay for different combinations of parameter values, we have come up with the optimized CNTFET parameters that give the minimum delay in Table 8.

Power Optimization for CNTFET
With advancement in processors and high-performance machines, the processors are expected to perform at higher speeds with low power. But increasing frequency for better performance comes with a challenge of power consumption which results into increase in device temperature. Due to the Short Channel Effect (SCE), the channel length in MOS transistors comes to a limit. With reduced effective channel length, there is also an increase in leakage current in MOS transistors. At the same time, CNTFET shows better performance with the decrease in size of channel length due to the ballistic transport of carriers. Moreover, shortening of channel length is not responsible for leakage current and SCE in CNTFET. In CNTFET, with the variation of different parameters such as chirality, diameter, and Pitch, there is a significant increase in transistor behavior. Increasing the value of the chiral vector or diameter reduces the bandgap, which increases the on-current of the transistor. But, in contrast, this also increases the leakage current in the off state for CNTFET [14]. The ambipolar transport and gate-induced drain leakage due to electron tunneling across the drain side are responsible for the leakage current in Schottky Barrier CNTFETs.
The vital parameter in lowering the leakage current is the threshold voltage, which is dependent on the energy gap (The gap between the Valence Band and the Conduction Band) of the semiconducting material. The chirality (Chiral vector) of PFET and NFET in CNT devices can have different values, and the difference in these values also affects the value of threshold voltage. This increases the high ON-Current but also increases the OFF-Leakage current [15,16]. But, as stated earlier, the design of CNTFET is complex, and its characteristics change effectively with changes in parameters such as channel length, diameter, pitch, chirality, and Tox (Oxide Thickness). So, to obtain the optimized CNTFET device that shows good performance in terms of dynamic power, we have simulated the design, and power for each parameter is calculated. MOSFET Dynamic power consumption is shown in Table 9, and CNTFET power consumption for varying parameters is shown in Tables 10-14. We have compared the dynamic power consumption values in CMOS transistors with unoptimized CNTFET. Afterward, we have gone through several experiments by changing the parameters to get superior performance in CNTFET. The results are summarized in Table 15.

Power-Delay Product
Power delay product (PDP) is considered the best measure to evaluate the performance of the device, considering both the power consumption and propagation delay of transistors [17]. We have used the delay and power results to get the value of PDP, and the best combination of parameters that result in minimum PDP can be used to make the combinational circuit. Lastly, optimized CNTFET is compared with the unoptimized model and traditional MOSFET transistors. As shown in Tables 16-21, we observed the effect of Chirality, Oxide thickness, dielectric constant, pitch, and the number of tubes on PDP. The lowest PDP for NAND, NOR, and NOT gates are recorded and compared to MOSFET devices. As PDP, accounts for switching time and power consumption in switching, that is considering the speed and performance of the device, it is considered one of the best measures to evaluate device performance. We can see, pitch, the number of tubes, and chirality have a significant impact on PDP compared to dielectric material thickness and constant.

Journal of Electronics and Electrical Engineering
After going through all the extensive simulations of power consumption and delay for these three logic gates and calculating the PDP based on the results, we have the optimized parameters with the lowest PDP value for all three gates shown in Table 22.
The following Figures 1-5 depict the variation in PDP by changing various CNTFET parameters for NAND, NOR and NOT gate. We can see a decreasing trend in PDP as we increase the chirality of the CNTs.

Conclusion and Future Works
We have done intensive simulations on basic logic gates derived from CNTFET and MOSFET transistors to evaluate the performance of evolving technology CNT-based transistors to keep up with Moore's law. The CNTFET devices without optimization show comparatively lower performance than traditional silicon based MOSFET transistors. But, after optimizing the parameters namely Chirality, Oxide thickness, dielectric constant, Pitch, and the number of tubes with respect to propagation delay and power dissipation, we get a better performing device with CNTFET over MOSFET.
The CNTFET transistors have many advantages over silicon transistors, but still, it is challenging to make IC derived of CNTFET transistors. We have calculated the optimum parameters for CNTFET-based logic gates for best performance. Also, simulation on identical chirality for both P and N-type CNTFET is performed, but in upcoming research, we will also consider dual chirality to optimize the power consumption in CNTFET devices. The optimum parameters for logic gates we obtained in this research might change for the combinational circuit, so we will be conducting research based on different combinational circuits to observe the behavior of transistors. Furthermore, we will evaluate the performance of other evolving technology such as FinFET, Silicon-On-Insulator Field Effect transistors (SOIFET), and GNRFET based transistors.