On-Wafer Drain Current Variability in GaN MIS-HEMT on 200-mm Silicon Substrates

: In this study, a detailed on-wafer (or global) variability analysis of drain current characteristics of GaN MIS-HEMT devices grown on 200 mm silicon substrate is conducted. For the first time to our knowledge, the on-wafer variability sources in GaN technologies due to the manufacturing process are investigated by combining experimental data and analytical variability modeling. The key parameters which affect the variability are oxide the interface charge fluctuations, the mobility fluctuations, the gate oxide thickness and/or the gate area variations and the access resistance fluctuations in the contact as well as in the 2DEG regions (source and drain sides). Due the specificity of GaN MIS HEMT device engineering process, we show that their variability performances are not, for the time being, comparable to the state-of-the art silicon CMOS technologies, and this can be valuable for reliable improvement and optimization of GaN technology fabrication process. This study has been verified over a large range of channel gate lengths for three normally-off GaN MIS-HEMT wafers and having different gate process flows.


Introduction
Heterojunction device-based AlGaN/GaN high electron mobility transistors (HEMTs) have attracted a lot of attention in the last decade in power electronics and RF applications [1]. Their performances require a high breakdown voltage, high electron mobility at AlGaN/GaN interface, low ON-resistance, high operating temperature and for RF application, a high field saturation speed and low parasitic capacity [2][3][4][5][6]. As the manufacturing fabrication volumes of GaN HEMT devices increase, it is necessary to analyse the variability of transistor electrical performances due to the fabrication process variation. Such on-wafer or global variability studies are useful for development and process engineer. Development engineers can use this methodology to analyse the sensitivity of process variations on electrical performance and tune the manufacturing process accordingly. Design of a significant number of GaN components on the same wafer are generally done with an objective to realize the same performance. In the reality, they have different electrical properties which depend on their fabrication process and their position on the same wafer (200 mm in this work) or from wafer to wafer. However, following the progressive miniaturization of GaN devices for power electronics or RF-circuit, the variability performances must be considered to obtain a reliable manufacturing process. For silicon technology, Mizuno et al. [7] have shown experimentally that the Vth fluctuations depend on the channel length and the gate oxide thickness. However, they demonstrated that Vth fluctuations are directly correlated with the dopant number fluctuations in the channel region. Various methodologies to analyse local and global variability have been proposed [8][9][10][11], but this is less the case for GaN devices.
In previous studies [12], a statistical characterization and statistical extraction of electrical parameters was presented for the same type of GaN MIS-HEMT devices. We apply here, for the first time, a methodology generally used in silicon technologies to analyse the variability of intrinsic electrical parameters such as drain current as well as the access resistance, gain parameter and threshold voltage [9]. Thus, the aim of this study is to employ this approach to analyse the on-wafer variability on Id-Vg characteristics of the GaN MIS-HEMT devices with recessed gate, and to discriminate the contribution of the active channel and of the source-drain access resistances. This will be useful to improve the manufacturing process of GaN MIS-HEMT technologies. We will first describe the studied wafers, device architecture and electrical characterization protocol. Next, we will recall electrical characterization of GaN MIS-HEMT and their influence on the effective gate length of the HEMT devices [5,12]. A global variability analysis is then performed between different gate length and different wafers. All experimental data are well fitted by the variability models which were used previously in silicon technologies. Finally, we will compare the parameter variability extracted in this work with those from best silicon technologies.

Devices and Experiment Methods
Electrical measurements were performed on different wafers processed with GaN MIS-HEMT technology with a fully recess depth (RD>tAlGaN) to ensure normally-off mode ( Figure 1a). GaN epitaxy is performed by Metal-Organic-Chemical Vapor Deposition (MOCVD), on 200 mm diameter silicon (111) substrates. The structure is composed of an AlN nucleation layer, an AlGaN based buffer, C-doped GaN buffer layers to ensure a high breakdown voltage, then an unintentionally doped (UID) GaN channel in which a back-barrier (doped layer) can be inserted. The total epitaxy layer thickness is about 4 µm. The piezoelectric effect to form the 2D electron gas (2DEG) is obtained with the growth of AlN spacer and an AlxGa1-xN barrier layer on top of the GaN channel layer, followed by in-situ deposition of a passivation layer [13,14].
The fully recessed Metal-Insulator Semiconductor (MIS) HEMT are processed by dry etching of AlGaN and UID-GaN layers in the gate area and Al2O3 gate oxide are processed by Atomic Layer Deposition (ALD) or by plasma enhanced atomic layer deposition PEALD in which AlN oxide spacer can be inserted (Figure 1a and 1b) to give an equivalent gate oxide thickness Al2O3/AlN [15]. The GaN channel in the recessed region, under the gate oxide presents a particular shape formed of the gate sidewalls with a specific angle, the gate corners and the gate bottom. Figure 1c shows a cross sectional TEM of the fully recessed MIS gate region with different typical interfaces. The test structures reported in this study were fabricated using three different process flows. The differences consist mainly in the fabrication steps such as optimization of the ohmic contacts process, the gate etching process and MIS gate depositions recipe. Wafers 1, 2 and 3 correspond to two different recess depths, a shallow gate recess (RD1) and a deep gate recess (RD2) [RD1<RD2]. Wafers 2 and 3 have approximatively the same recess depth RD2. Notice that, the etching process on the gate region can affect the electrostatics control of channel layer in this region, but the source-drain access resistance remains the same. The source and drain are composed of metallic Ohmic contacts (Ti/AlCu) connected to the 2D electron gas (2DEG) formed at the AlGaN/GaN interface. The symmetrical tested devices were T-metal gate only with same gate field plate length on the source and drain sides such as LFPg = 0.25 µm. The different gate lengths for wafers #1 and #2 (RD1 and RD2, respectively) varying from 0.5 to 10 µm and with the same width (W = 100 µm), and for wafer #3, the gate lengths varying from 0.25 µm, 2 µm and 200 µm width ( Table 1). The source-gate and drain-gate lengths are equal (Lgs = Lgd = 2 µm). The Id-Vg transfer characteristics were measured in linear regime (Vd < kT/q) using an B1500 Semiconductor Device Analyser. The Cgc-Vg characteristics were measured by split CV method owing to an HP 4284 LCR meter at a frequency of 10 kHz for short channel and 1 kHz for long channel to avoid channel response time and trap response effects, specific to GaN MIS-HEMT devices. The GaN MIS-HEMTs parameters extraction was carried out using the Y-function based protocol, which allowed to evaluate the source-drain access resistance values and to remove their influence on the Id-Vg transfer characteristics and mobility. This method was originally developed for Si-MOSFETs [16] and recently applied and validated on MIS-HEMT GaN devices at room temperature [12,17], then, at different temperatures down to deep cryogenic temperatures [18]. The Y-function is defined from drain current Id and transconductance gm by: In strong inversion, the Y-function has a linear behaviour such as ( ) WCoxμ0/L is the transconductance parameter, Cox is the intrinsic gate oxide capacitance, μ0 is the low field mobility and Vth the threshold voltage without source-drain access resistance effect. The source-drain access resistance is then extracted on each HEMT device, in linear operation and from the asymptotic behaviour parallel to the x axis (plateau) of the quantity defined below plotted in the strong inversion region. Figure 2 shows typical statistical set of drain current Id(Vg) characteristics as a function of the gate voltage obtained on 25 devices of wafer #1 and wafer #2 at 25°C. The dispersion of the characteristics observed in Figure 2a in strong inversion regime is known to result from the degraded source and drain ohmic contact resistance [12].   Using source-drain access resistance RSD values extracted previously from Eq. (2), the Id(Vg) characteristics and effective mobility μsplit(Nch) can be corrected according to the Eqs (3) and (4), respectively:

Transfer Characteristics and Electrical Parameters
where μsplit(Nch) = L·Id(Vg)/W·Vd·Qch(Vg) is the classical split-CV mobility, Qch = q·Nch is the total channel charge obtained from the integration of Cgc-Vg characteristics. Figure 4 shows the Id(Vg) characteristics of raw data for wafer 1 without ( Figure 4a) and with (Figure 4b) source-drain series resistance correction in linear regime (Vd = 10 mV). The impact of source-drain access resistance RSD can be clearly seen from the Id-Vg characteristics of GaN MIS-HEMT devices for wafer #1 (see Figure 4a), where the curve dispersion is small in near-threshold region but huge in strong inversion region. After source-drain access resistance effects removing, these dispersions are greatly reduced (see Figure 4b).
The split-CV effective mobility variations with channel length obtained without and with source-drain access resistance are shown in Figure 4c. It also clearly confirms that the mobility value dispersion before correction is really due to the source-drain access resistance variations.
Moreover, the mean values of the drain current characteristics Id(Vg) in linear regime were fitted with Eq.
where the channel charge Qch is computed from weak to strong inversion using Lambert compact model as, where kBT/q is the thermal voltage, n is the ideality factor which can be obtained from the subthreshold slope, LW is the Lambert-W function [19], Vth is the threshold voltage and Cox the intrinsic gate oxide capacitance. The effective mobility taking into account the influence of the source-drain access regions is given by Eq. (7), where 0  is the low field mobility, 1 is the first order mobility attenuation coefficients, 0  being the intrinsic first order mobility attenuation factor (around 0.03 V -1 here) and factor. Figures 5a and 5b show the best fit of typical drain current transfer characteristics Id-Vg in linear regime for different wafers. The corresponding transconductance gm-Vg and Y-Vg characteristics (experimental and modeling) are shown in Figure 5c and 5d, illustrating a larger maximum transconductance on wafer #3 and a larger slope of Y-function in strong inversion due to the higher mobility. Note that the Y-functions are almost identical for wafers #1 and #2 due to the same intrinsic mobility. However, we can see from Figure 5c a larger slope on normalised Y-function characteristics for wafer #3 as compared to wafer #1 and #2.  Figure 6 shows the mean values of the intrinsic channel mobility characteristics μeff(Nch) for different wafers #1, #2 and #3 measured on GaN MIS-HEMT by split CV technique. We can see that, for wafers #1 and #2, we have the same mobility value for the Al2O3/GaN interface, whereas it is significantly improved for the Al2O3/AlN/GaN interface in wafer #3, due to the interposition of the AlN oxide spacer layer.

Drain current Global variability Methodology
We have shown previously a statistical extraction methodology of intrinsic electrical parameter from the Id-Vg curves [12]. This enabled us to show that it is possible to remove for each GaN MIS-HEMT device the source-drain access resistance effect on the intrinsic parameters of the active channel. In classical GaN technology study, these extracted parameters can be screened for devices placed in different regions all over the wafer or on different wafers. Here, we explored the global or on-wafer variability of the drain current and Y-function characteristics measured on 200 mm GaN/Si wafers using, for the first time, the methodology that was originally developed for Si-MOSFETs based on the analysis of the drain current standard deviation characteristics as a function of gate voltage Vg.  For wafer #1, we observe an increase of the global drain current variability ΔId /Id in strong inversion when the gate bias is increased (see Figure 7a), whereas the global variability on wafer #2 and #3 decreases or remains constant above threshold (see Figure 7b and 7c, respectively). This is because the drain current variability is dominated in strong inversion by the source-drain access resistance variability. This will be confirmed below by the standard deviation analysis.
To better quantify and analyse the variability of the drain current and the Y-function (defined in Eq. (1)), we can compute respectively the standard deviation associated to their global variability ( / )   d d I I and ( / )  Y Y . To this end, following [9][10][11], a sensitivity analysis of the drain current function variables can be carried out as in Eqs (9) and (10) (11) and (12) [9][10][11].
where ( ), V mainly stems from fluctuations in channel doping level and/or gate oxide interface charges and has a larger influence near and below threshold [7][8][9][10][11].
The drain current standard deviations versus gate voltage curves are shown in Figure 8 (symbols) for GaN MIS-HEMTs for different gate lengths and wafers. The best fit characteristics (dashed line) obtained with the variability model of Eq. (11) are also reported in the same graphs corresponding to each wafer. This model enables to extract a set of three variability parameters such as ( ), In strong inversion region, Figure 8a shows an increase of standard deviation ( / )   d d I I level with gate bias due to the variability impact of source-drain access resistances ( ).
This increase depends on the gate length and is less pronounced for long channel length (50 µm) as compared to short channel one (0.5 µm, Figure 8a). This phenomenon disappears on wafers #2 (Figure 8b) and #3 (Figure 8c) thanks to the optimized ohmic contact fabrication process. However, the wafers #2 and #3 are more sensitive to the variability of gain factor ( / )    The standard deviation of variability dependence with gate length around threshold shows different levels for the various wafers. Compared to wafers #1 and #2, wafer #3 presents a higher level of the standard deviation ( / )   d d I I of about a half-decade below the threshold (  g th has a largest impact in subthreshold region, as mentioned previously. Instead, for wafer #2 and #3, ( / )     is predominant in strong inversion and its contribution is even larger for higher gate bias, because the access resistance variability contribution is reduced since the value of their HEMT access resistance is smaller.
In Figure 9 we summarized different variability parameters ( ), which were extracted by modelling on wafers #1, #2 and #3. As suggested previously from drain current standard deviation characteristics, a higher variability of threshold voltage ( )   th V is obtained on wafer #3 as compared to wafers #2 and #3 (Figure 9a). However, the variability of current gain parameter ( / )     is estimated between 1 and 10 (%) for all wafers (Figure 9b). Compared to the wafer #2 and #3, wafer #1 shows the largest (up to 2 decades) variability of source-drain access resistance ( )   SD R in line with its higher mean value and likely due to the degraded ohmic contacts fabrication process (Figure 9c). Note that, for GaN technologies, a larger variability of the threshold voltage ( )   th V could originate as for silicon technologies from prevailing role of channel doping variability and/or oxide interface charges fluctuations. This phenomenon is larger for small gate lengths and/or large device widths due to the increased contribution of the gate sidewalls (or gate corners) on the overall device operation.  Another interesting parameter in variability analysis is the so-called input referred global variability parameter. It gives a best observation between the variability results and can be made by plotting the input referred global variability parameter versus gate bias. This input referred global variability parameter is defined by [9][10][11]: Figure 11 shows the input referred global variability parameter   g V versus gate bias for different gate lengths and for different wafers #1 (Figure 11a), #2 (Figure 11b), and #3 (Figure 11c). The input referred global variability parameter shows a plateau at low gate bias close to threshold and below, whose value is approximately given by    The standard deviation of th V variability can be advantageously converted into a standard deviation of the oxide interface charge fluctuation   ss Q (see Eq. 14) in order to estimate their amplitude. 2 4 10 /   q cm ) [7][8][9][10][11]. This is likely due to the lack of maturity of such research-level GaN MIS-HEMT technology and indicates that much improvement could be made after proper process optimization in the future. Finally, the contribution of channel resistance variability to the total variability of the GaN MIS-HEMT devices %CH can be evaluated using the variability model of Eq. (11) as [9][10][11]:  Figure 12 shows typical variations of the channel contribution %CH (respectively, source-drain access resistance contribution %SD 1 %CH   ) versus gate voltage. As expected, it clearly indicates that wafer #1 suffer more source-drain access resistance variability than wafers #2 and #3.

Conclusion
In this work, a detailed study of global variability of the GaN MIS-HEMTs drain current characteristics on 200-mm silicon wafers has been presented here for the first time. The main global variability parameters of GaN MIS-HEMT technology have been extracted using experimental data and the analytical global variability model initially developed for Silicon technology. The global variability analysis is also used on Y-function characteristics showing thus the intrinsic channel variability parameters such as for threshold voltage and gain parameter. The results also show that the variability performances found on different GaN/Si MIS-HEMTs from 200-mm wafers are not as good as those achieved in Silicon CMOS technologies. The key parameters which affect the variability are the oxide interface charge fluctuations, the mobility fluctuations, the gate oxide thickness and/or the gate area variations and access resistance fluctuations in the contact as well as in the 2DEG regions (source and drain sides). This reveals that such research-level GaN/Si MIS-HEMT technology has not reached their full maturity and that much improvement margins are possible after proper GaN technology process optimization.