HOU, Z.; WANG, X.; YI, Y. A Schematic-Level Digital Near-Memory Computing Architecture Utilizing 1T3R Memristor Arrays and Pipelined MAC for Pattern Recognition. Journal of Electronics and Electrical Engineering, Singapore, v. 5, n. 2, p. 411–426, 2026. DOI: 10.37256/jeee.52202610117. Disponível em: https://ojs.wiserpub.com/index.php/JEEE/article/view/10117. Acesso em: 14 sep. 2026.