1.
Hou Z, Wang X, Yi Y. A Schematic-Level Digital Near-Memory Computing Architecture Utilizing 1T3R Memristor Arrays and Pipelined MAC for Pattern Recognition. J. Electron. Electric. Eng. [Internet]. 2026 Aug. 19 [cited 2026 Sep. 14];5(2):411-26. Available from: https://ojs.wiserpub.com/index.php/JEEE/article/view/10117