In Depth Parasitic Capacitance Analysis on GaN-HEMTs with Recessed MIS Gate

Authors

  • Romeo Kom Kammeugne 1. Université Grenoble Alpes, CEA-LETI, MINATEC Campus, F-38054, Grenoble, France; 2. Université Grenoble Alpes, Université Savoie Mont Blanc, CNRS, Grenoble INP, IMEP-LAHC, 38000, Grenoble, France
  • Charles Leroux Université Grenoble Alpes, CEA-LETI, MINATEC Campus, F-38054, Grenoble, France
  • Tadeu Mota Frutuoso Université Grenoble Alpes, CEA-LETI, MINATEC Campus, F-38054, Grenoble, France
  • Jacques Cluzel Université Grenoble Alpes, CEA-LETI, MINATEC Campus, F-38054, Grenoble, France
  • Laura Vauche Université Grenoble Alpes, CEA-LETI, MINATEC Campus, F-38054, Grenoble, France
  • Romain Gwoziecki Université Grenoble Alpes, CEA-LETI, MINATEC Campus, F-38054, Grenoble, France
  • Xavier Garros Université Grenoble Alpes, CEA-LETI, MINATEC Campus, F-38054, Grenoble, France
  • Matthew Charles Université Grenoble Alpes, CEA-LETI, MINATEC Campus, F-38054, Grenoble, France
  • Edwige Bano Université Grenoble Alpes, Université Savoie Mont Blanc, CNRS, Grenoble INP, IMEP-LAHC, 38000, Grenoble, France
  • Gerard Ghibaudo Université Grenoble Alpes, Université Savoie Mont Blanc, CNRS, Grenoble INP, IMEP-LAHC, 38000, Grenoble, France

DOI:

https://doi.org/10.37256/jeee01010003

Keywords:

electrical characterization, modeling, power semiconductor devices, gate length, recess depth, normally-off, HEMT, GaN, 2DEG, parasitic capacitance, 2D Simulation

Abstract

In this study, parasitic coupling capacitance behavior on GaN devices with recessed MIS-gate is analysed in depth by combining experimental data, 2D-simulations, analytical calculations, and TEM imaging. This enabled to highlight the second channel formation. A new analytical model to determine the contribution of the active channel and the different coupling parasitic capacitances from a gate-to-channel capacitance Cgc curve of a GaN MIS-HEMT is proposed. This also enables the evaluation of the respective contribu-tions of all components such as the passivation layer and gate field plate capacitances in the parasitic ca-pacitance and effective gate length evaluation of GaN devices with recessed MIS gate, which could be useful for reliable parameter extraction, device modeling and optimization.

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Published

2022-10-18

How to Cite

(1)
Kammeugne, R. K.; Leroux, C.; Frutuoso, T. M.; Cluzel, J.; Vauche, L.; Gwoziecki, R.; Garros, X.; Charles, M.; Bano, E.; Ghibaudo, G. . In Depth Parasitic Capacitance Analysis on GaN-HEMTs With Recessed MIS Gate. J. Electron. Electric. Eng. 2022, 1, 3.