In Depth Parasitic Capacitance Analysis on GaN-HEMTs with Recessed MIS Gate
DOI:
https://doi.org/10.37256/jeee.1120221684Keywords:
electrical characterization, modeling, power semiconductor devices, gate length, recess depth, normally-off, HEMT, GaN, 2DEG, parasitic capacitance, 2D SimulationAbstract
In this study, parasitic coupling capacitance behavior on GaN devices with recessed MIS-gate is analysed in depth by combining experimental data, 2D-simulations, analytical calculations, and TEM imaging. This enabled to highlight the second channel formation. A new analytical model to determine the contribution of the active channel and the different coupling parasitic capacitances from a gate-to-channel capacitance Cgc curve of a GaN MIS-HEMT is proposed. This also enables the evaluation of the respective contribu-tions of all components such as the passivation layer and gate field plate capacitances in the parasitic ca-pacitance and effective gate length evaluation of GaN devices with recessed MIS gate, which could be useful for reliable parameter extraction, device modeling and optimization.
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Copyright (c) 2022 Romeo Kom Kammeugne, et al.
This work is licensed under a Creative Commons Attribution 4.0 International License.